By Jacob Garby


2019-02-06 23:44:51 8 Comments

I've found the following schematic:

Z80 schematic

Which after a lot of datasheet reading I mostly understand.

The main thing I don't understand, however, is what's going on with the RESET pin. First of all, I understand that the RESET pin is active-low. In this case, why is it pulled high to +5V? Surely I wouldn't want the CPU to reset. I assume the answer to this part is something to do with resetting on boot.

My main question is why there's a capacitor from RESET to (what seems to be) ground.

Is that even ground? If so, why is there a capacitor before it? If not, what is it, and what does it do?

2 comments

@Jack Creasey 2019-02-06 23:54:43

The Reset pin is Active low, so has to be pulled low to reset the processor.

The capacitor connected to the reset pin is also connected to Gnd (the schematic uses a wrong symbol), and along with the pullup resistor forms an RC network that holds the processor in reset for a time after VCC first rises.

You will often see Reset circuits such as this:

schematic

simulate this circuit – Schematic created using CircuitLab

The RC values are defined to hold the processor in reset long enough to let the supply stabilize. It can also provide a physical reset button to reset/restart the processor.

@Technophile 2019-02-07 03:13:23

Often there is also a diode in parallel with R1, to discharge C1 when VCC is removed.

@Jack Creasey 2019-02-07 04:11:08

@Technophile Quite right ...I added it to the schematic

@WhatRoughBeast 2019-02-07 04:32:34

Also, for proper operation this requires that the input be a Schmitt trigger, in order to allow reliable operation.

@Jack Creasey 2019-02-07 05:41:47

@WhatRoughBeast Some circuits did use a Schmidt trigger some didn't. Many circuits didn't even have C1. The *Reset input was the same as the *NMI and *INT pins and was level sensitive, so as VCC rose it eventually released the *Reset. But I do agree the better schematics did do it that way.

@Transistor 2019-02-07 00:00:12

As you have correctly stated, RESET is active low.

On power up C is discharged, the reset is held low which forces the chip to hold off initialising while the power stabilises.

After a time roughly equal to R x C (s) the capacitor voltage has charged up through R enough to release the RESET and allow the controller to run. By this time the power should be stable.

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